Alphabetic Trees Theory and Applications in Layout Driven Logic Synthesis Revision of TCAD Manuscript

Routing plays an important role in determining the total circuit area and circuit performance and hence must be addressed as early as possible during the design process In this paper an e ective routing driven approach for technology dependent logic synthesis which relies on alphabetic tree construction is presented Alphabetic trees are trees which are generated under the restriction that the initial order on the leaf nodes is maintained while not introducing any internal edge crossing First a mechanism for generating all alphabetic trees on a given number of leaf nodes is presented Next the number of such trees is calculated under di erent height and degree restriction and used to derive upper bounds on the complexity of alphabetic tree optimization problem A classi cation of tree cost functions for which alphabetic trees can be generated in polynomial time is also proposed Speci cally alphabetic tree optimization algorithms are applied to generate optimal alphabetic fanout trees For fanout optimization we obtained improvement in chip area at the cost of loss in performance